In a nonvolatile semiconductor storage device, specially, a highly-integrated memory such as a flash memory, a demand for high integration of memory elements (memory cells) is increasing, and a product in which a fine element whose minimum feature size is about 30 nm or less is used has been developed. Improvement of integration by reducing the minimum feature size is reaching a physical limit such as increase in variation of a transistor operation in the element, and is reaching an economic limit such as rapid increase in cost for a lithography process and a fabrication process. Therefore, it is required to introduce a technology of arranging the memory elements (memory cells) three-dimensionally for realizing higher integration.
In the three-dimensional array of the memory cells (transistors), if the interval between the transistors adjacent in a vertical direction is made small for improving an arrangement density of the memory cells (transistors), interference between the transistors adjacent in the vertical direction cannot be ignored. Consequently, the transistor may malfunction.
On the other hand, if the interval between the transistors adjacent in the vertical direction is made large for attenuating the interference between the transistors adjacent in the vertical direction, it becomes difficult to improve the arrangement density of the memory cells (transistors).